A Multiple Level Network Approach for Clock Skew Minimization Under Process Variations
نویسندگان
چکیده
In this paper, we investigate the effect of multilevel networks on clock skew. We first define the simplified RC circuit model of a hybrid clock mesh/tree structure. The skew reduction effects of shunt segments contributed by the mesh is derived analytically from the simplified model. The result indicates that the skew decreases proportionally to the exponential of −Rs/R, where Rs is the driving resistance of the clock buffer at a leaf node in the clock tree and R is the resistance of a mesh segment. Based on our analysis, we propose a hybrid multi-level mesh and tree structure for global clock distribution. A simple optimization scheme is adopted to optimize the routing resource distribution of the multi-level mesh. Experimental results show that by adding a mesh to the bottom-level leaves of an H-tree, the clock skew can be reduced from 29.2 ps to 8.7 ps, and the multi-level networks with same total routing area can further reduce the clock skew by another 30%. We also discuss the inductive effect of the mesh. When the clock frequency is less than 2 GHz, the RC model remains valid for clock meshes with grounded shielding or using differential signals. H. Chen, B. Yao, and C.K. Cheng are with department of computer science and engineering, University of California, San Diego. M. Mori is currently with Fujitsu Inc., Japan. His work was performed while he was with the department of computer science and engineering, University of California, San Diego
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